Yili Xu*, Xin Li, Xiaodong Yin, Guowei Zhang, Jingyi Li, Qianqian Liu
Hangzhou Puxi Optoelectronic Semiconductor Technology Co., Ltd., Hangzhou 31700, Zhejiang, China.
*Corresponding author: Yili Xu
References
[1] Wu J. Research on control and integration technology of new power devices [dissertation]. Chengdu: University of Electronic Science and Technology of China; 2019. doi:10.27005/d.cnki.gdzku.2019.000006
[2] Zhou R, Feng S, Wu J, et al. SiC MOSFET research progress. J Bohai Univ (Nat Sci Ed). 2024;45(3):230-40. doi:10.13831/j.cnki.issn.1673-0569.2024.03.001
[3] Xu Z. The market size of SiC devices is expected to reach $7 billion in 2027. China Electron News. 2022 Apr 12;(008). doi:10.28065/n.cnki.ncdzb.2022.001289
[4] Luo Y. The elimination of silicon carbide: price competition, giant adjustment. 21st Century Bus Herald. 2025 Jan 23;(010). doi:10.28723/n.cnki.nsjbd.2025.000319
[5] Qu K, Huai Y, Liu J. Design of low voltage VDMOSFET cell size. Microelectron Comput. 2007;24(12):77-79,84.
[6] Hu J. Device design and key process research of 4H-SiC UMOS [dissertation]. Chengdu: University of Electronic Science and Technology of China; 2015.
[7] Hu J, Deng X, Shen H, et al. Study on 4H-SiC trench process of ICP etching. J Vac Sci Technol. 2015;35(5):570-4.
[8] Dong Z, Liu H, Zeng C, et al. Improvement of morphology of 4H-SiC deep trench etching. Res Prog Solid State Electron. 2022;42(3):239-43.
[9] Yao D. Study on the performance of improved 4H-SiC ultra-junction trough MOSFET structure [dissertation]. Guiyang: Guizhou University; 2024. doi:10.27047/d.cnki.ggudu.2024.003144
[10] Gao Y. SiC VDMOS research on device structure design and interface trap effect [dissertation]. Chengdu: University of Electronic Science and Technology of China; 2013.
[11] Qu K, Huai Y, Liu J. Design of low voltage VDMOSFET cell size. Microelectron Comput. 2007;24(12):77-79,84.
[12] Gao Y. VDMOSFET optimal design of conduction resistance. Aircr Des. 2002;22(2):48-51.
[13] Li S, Yang X, Huang R, et al. Design and preparation of 15 kV/10 A SiC power MOSFET devices. Res Prog Solid State Electron. 2021;41(2):93-7.
[14] Zhu F, Zhang X, Zhang H. Formation mechanism of multi-functional black silicon based on optimized deep reactive ion etching technique with SF6/C4F8. Sci China Technol Sci. 2015;58(2):381-9.
[15] Zhang Y, Huang R, Bai S. An improved 4H-SiC ultra junction UMOS device. Power Electron. 2024;22(S01):254-60.
[16] Fu X, Liu J, Xue J, et al. A POA optimization process for SiC MOSFET gate oxygen interface defects. Semicond Technol.
[17] Xu Y, et al. Studies on the structure of the U-groove vdmosfet devices. Probe Environ Sci Technol. 2024;6(4).
How to cite this paper
Sub-micron Cell Design and Process Fault Tolerance of Source Buried Trench Silicon Carbide VDMOSFET
How to cite this paper: Yili Xu, Xin Li, Xiaodong Yin, Guowei Zhang, Jingyi Li, Qianqian Liu. (2025). Sub-micron Cell Design and Process Fault Tolerance of Source Buried Trench Silicon Carbide VDMOSFET. Engineering Advances, 5(2), 76-81.
DOI: http://dx.doi.org/10.26855/ea.2025.04.006